우리는 귀하의 프라이버시를 소중히 여깁니다
"모든 쿠키 허용"을 클릭하면 사이트 탐색을 개선하고, 사이트 사용을 분석하며, 마케팅 및 성능 노력에 도움을 주기 위해 쿠키를 귀하의 장치에 저장하는 데 동의한 것으로 간주됩니다. 이 주제에 대한 추가 정보는 당사의 정책에서 확인할 수 있습니다. 개인정보 보호정책
도면
사양
일반 사양
| 항목 | 치수 | 단위 |
|---|---|---|
| 도트 매트릭스 (해상도) | 128 × 64 | 점 |
| 모듈 치수 | 77.2 × 42.14 ×3.4 | mm |
| 활성 영역 | 55.01 × 27.49 | mm |
| 도트 크기 | 0.40 × 0.40 | mm |
| 도트 피치 | 0.43 × 0.43 | mm |
| 디스플레이 모드 | 패시브 매트릭스 | |
| 디스플레이 색상 | Monochrome | |
| Drive Duty | 1/64 Duty | |
| IC | SSD1309 | |
| 인터페이스 | 6800,8080,SPI,I2C | |
| 크기 (대각선) | 2.42 인치 | |
절대 최대 정격값
| Parameter | 기호 | 최소값 | 최대값 | 단위 |
|---|---|---|---|---|
| Supply Voltage for Logic | VDD | -0.3 | 4 | V |
| Supply Voltage for Display | VCC | 0 | 15 | V |
| 작동 온도 | TOP | -40 | +80 | °C |
| 보관 온도 | TSTG | -40 | +85 | °C |
전기적 특성
DC 전기적 특성
| 항목 | 기호 | 조건 | 최소값 | 대표값 | 최대값 | 단위 |
|---|---|---|---|---|---|---|
| Supply Voltage for Logic | VDD | － | 2.8 | 3.0 | 3.3 | V |
| Supply Voltage for Display | VCC | － | 12.5 | 13.0 | 13.5 | V |
| High Level Input | VIH | － | 0.8×VDD | － | VDD | V |
| Low Level Input | VIL | － | 0 | － | 0.2×VDD | V |
| High Level Output | VOH | － | 0.9×VDD | － | VDD | V |
| Low Level Output | VOL | － | 0 | － | 0.1×VDD | V |
| 50% Check Board operating Current | VCC =13V | - | 29 | 43.5 | mA | |
인터페이스 핀 기능
| Pin No. | 기호 | 기능 |
|---|---|---|
| 1 | NC(Vss) | No connection (ground.) |
| 2 | VCC | Power supply for panel driving voltage. This is also the most positive power voltage supply pin. |
| 3 | VCOMH | COM signal deselected voltage level. A capacitor should be connected between this pin and VSS. |
| 4 | IREF | This pin is the segment output current reference pin. IREF is supplied externally. A resistor should be connected between this pin and VSS to maintain the current around 10uA. Please refer to Figure 8-15 for the details of resistor value |
| 5~12 | D7~D0 | These pins are bi-directional data bus connecting to the MCU data bus. Unused pins are recommended to tie LOW. When serial interface mode is selected, D0 will be the serial clock input: SCLK; D1 will be the serial data input: SDIN and D2 should be kept NC. When I2C mode is selected, D2, D1 should be tied together and serve as SDAout, SDAin in application and D0 is the serial clock input, SCL. |
| 13 | E/RD# | This pin is MCU interface input. When 6800 interface mode is selected, this pin will be used as the Enable (E) signal. Read/write operation is initiated when this pin is pulled HIGH and the chip is selected. When 8080 interface mode is selected, this pin receives the Read (RD#) signal. Read operation is initiated when this pin is pulled LOW and the chip is selected. When serial or I2C interface is selected, this pin must be connected to VSS. |
| 14 | R/W# | This pin is read / write control input pin connecting to the MCU interface. When 6800 interface mode is selected, this pin will be used as Read/Write (R/W#) selection input. Read mode will be carried out when this pin is pulled HIGH and write mode when LOW. When 8080 interface mode is selected, this pin will be the Write (WR#) input. Data write operation is initiated when this pin is pulled LOW and the chip is selected. When serial or I2C interface is selected, this pin must be connected to VSS. |
| 15 | D/C# | This pin is Data/Command control pin connecting to the MCU. When the pin is pulled HIGH, the data at D[7:0] will be interpreted as data. When the pin is pulled LOW, the data at D[7:0] will be transferred to a command register. In I2C mode, this pin acts as SA0 for slave address selection. When 3-wire serial interface is selected, this pin must be connected to VSS. For detail relationship to MCU interface signals, refer to Timing Characteristics |
| 16 | RES# | This pin is reset signal input. When the pin is pulled LOW, initialization of the chip is executed. Keep this pin pull HIGH during normal operation. |
| 17 | CS# | This pin is the chip select input connecting to the MCU. The chip is enabled for MCU communication only when CS# is pulled LOW (active LOW). |
| 18 | NC | No connection |
| 19 | BS2 | MCU bus interface selection pins. Select appropriate logic setting as described in the following table.  Note (1) 0 is connected to VSS (2) 1 is connected to VDD |
| 20 | BS1 | |
| 21 | Vdd | Power supply pin for core logic operation |
| 22~28 | NC | No connection |
| 29 | Vss | Ground pin. It must be connected to external ground. |
| 30 | NC(Vss) | No connection (ground.) |