설명
도면
Data source of: WEO012864ABXPP3N0Y000
사양
인터페이스 핀 기능
| No. | 기호 | 기능 | ||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1 | N.C. (GND) | The supporting pins can reduce the influences from stresses on the function pins. These pins must be connected to external ground. | ||||||||||||||||||||||||
| 2 | C2P | C1P/C1N – Pin for charge pump capacitor; Connect to each other with a capacitor. C2P/C2N – Pin for charge pump capacitor; Connect to each other with a capacitor. |
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| 3 | C2N | |||||||||||||||||||||||||
| 4 | C1P | |||||||||||||||||||||||||
| 5 | C1N | |||||||||||||||||||||||||
| 6 | VBAT | This is the power supply pin for the internal buffer of the DC/DC voltage converter. It must be connected to external source when the converter is used. It should be connected to VDD when the converter is not used. | ||||||||||||||||||||||||
| 7 | NC | NC | ||||||||||||||||||||||||
| 8 | VSS | This is a ground pin. | ||||||||||||||||||||||||
| 9 | VDD | Power supply pin for core logic operation. | ||||||||||||||||||||||||
| 10 | BS0 | These pins are MCU interface selection input. See the following table:
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| 11 | BS1 | |||||||||||||||||||||||||
| 12 | BS2 | |||||||||||||||||||||||||
| 13 | CS# | This pin is the chip select input connecting to the MCU. The chip is enabled for MCU communication only when CS# is pulled LOW (active LOW). |
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| 14 | RES# | This pin is reset signal input. When the pin is low, initialization of the chip is executed. Keep this pin HIGH (i.e. connect to VDD) during normal operation. | ||||||||||||||||||||||||
| 15 | D/C# | This pin is Data/Command control pin connecting to the MCU. When the pin is pulled HIGH, the data at D[7:0] will be interpreted as data. When the pin is pulled LOW, the data at D[7:0] will be transferred to a command register. In I2C mode, this pin acts as SA0 for slave address selection. When 3-wire serial interface is selected, this pin must be connected to VSS. |
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| 16 | R/W# | This is read / write control input pin connecting to the MCU interface. When interfacing to a 6800-series microprocessor, this pin will be used as Read/Write (R/W#) selection input. Read mode will be carried out when this pin is pulled HIGH (i.e. connect to VDD) and write mode when LOW. When 8080 interface mode is selected, this pin will be the Write (WR#) input. Data write operation is initiated when this pin is pulled LOW and the chip is selected. When serial or I2C interface is selected, this pin must be connected to VSS. |
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| 17 | E/RD# | This pin is MCU interface input. When 6800 interface mode is selected, this pin will be used as the Enable (E) signal. Read/write operation is initiated when this pin is pulled HIGH and the chip is selected. When 8080 interface mode is selected, this pin receives the Read (RD#) signal. Read operation is initiated when this pin is pulled LOW and the chip is selected. When serial or I2C interface is selected, this pin must be connected to VSS. |
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| 18~25 | D0~D7 | These pins are bi-directional data bus connecting to the MCU data bus. Unused pins are recommended to tie LOW. When serial interface mode is selected, D2 should be either tied LOW or tied together with D1 as the serial data input: SDIN, and D0 will be the serial clock input: SCLK. When I2C mode is selected, D2, D1 should be tied together and serve as SDAout, SDAin in application and D0 is the serial clock input, SCL. |
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| 26 | IREF | When external IREF is used, a resistor should be connected between this pin and VSS to maintain the IREF current at a maximum of 30uA. When internal IREF is used, this pin should be kept NC. |
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| 27 | VCOMH | COM signal deselected voltage level. A capacitor should be connected between this pin and VSS. |
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| 28 | VCC | Power supply for panel driving voltage. This is also the most positive power voltage supply pin. When charge pump is enabled, a capacitor should be connected between this pin and VSS. |
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| 29 | VLSS | This is an analog ground pin. It should be connected to VSS externally. | ||||||||||||||||||||||||
| 30 | NC (GND) |
The supporting pins can reduce the influences from stresses on the function pins. These pins must be connected to external ground. |
기계적 데이터
| 항목 | 치수 | 단위 |
|---|---|---|
| 도트 매트릭스 | 128 × 64 Dots | － |
| 모듈 치수 | 24.7 × 16.59 × 1.26 | mm |
| 활성 영역 | 21.74 × 11.20 | mm |
| 도트 크기 | 0.15 × 0.15 | mm |
| 도트 피치 | 0.17 × 0.17 | mm |
| 디스플레이 모드 | 패시브 매트릭스 | |
| 디스플레이 색상 | 듀얼 컬러 (노란색 / 하늘색) | |
| Drive Duty | 1/64 Duty | |
| IC | SSD1315 | |
| 인터페이스 | 6800,8080,SPI,I2C | |
| 크기 (대각선) | 0.96 인치 | |
절대 최대 정격값
| Parameter | 기호 | 최소값 | 최대값 | 단위 |
|---|---|---|---|---|
| Supply Voltage for Logic | VDD | 0 | 4 | V |
| Charge Pump Regulator Supply Voltage | VBAT | -0.3 | 6.0 | V |
| Supply Voltage for Display | VCC | 0 | 18.0 | V |
| 작동 온도 | TOP | -30 | +70 | °C |
| 보관 온도 | TSTG | -30 | +70 | °C |
전기적 특성
DC 전기적 특성
| 항목 | 기호 | 조건 | 최소값 | 대표값 | 최대값 | 단위 |
|---|---|---|---|---|---|---|
| Supply Voltage for Logic | VDD | － | 1.65 | 3.0 | 3.3 | V |
| Supply Voltage for Display (Supplied Externally) |
VCC | － | 7.5 | 8.0 | 8.5 | V |
| Charge Pump Regulator Supply Voltage | VBAT | － | 3.0 | 3.5 | 4.2 | V |
| Charge Pump Output Voltage for Display (Generated by Internal DC/DC) | Charge Pump VCC |
－ | 7.0 | 7.5 | － | V |
| Input High Volt. | VIH | － | 0.8×VDD | － | VDD | V |
| Input Low Volt. | VIL | － | 0 | － | 0.2×VDD | V |
| Output High Volt. | VOH | － | 0.9×VDD | － | VDD | V |
| Output Low Volt. | VOL | － | 0 | － | 0.1×VDD | V |
| Operating Current for VCC (Display 50% Pixel on) (VCC Supplied Externally) |
ICC | VCC =8V | － | 5.0 | 7.5 | mA |
| Display 50% Pixel on (VCC Generated by Internal DC/DC) |
IBAT | VBAT=3.5V | － | 15 | 22.5 | mA |
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