Pin No. |
Symbol |
Level |
Beschreibung |
1 |
IRS |
I |
This terminal selects the resistors for the V0 voltage level adjustment.
IRS = “H”: Use the internal resistors
IRS = “L”: Do not use the internal resistors. The V0 voltage level is
regulated by an external resistive voltage divider attached to the VR terminal |
2 |
/HPM |
I |
This is the power control terminal for the power supply circuit for liquid crystal drive.
/HPM = “H”: Normal mode
/HPM = “L”: High power mode (Default) |
3 |
P/S |
I |
This is the parallel data input/serial data input switch terminal.
P/S = “H”: Parallel data input.
P/S = “L”: Serial data input.
The following applies depending on the P/S status:
P/S |
Data/Command |
Data |
Read/Write |
Serial Clock |
"H" |
A0 |
D0 to D7 |
/RD,/WR |
X |
"L" |
A0 |
SI(D7) |
Write only |
SCL(D6) |
When P/S = “L”, D0 to D5 fixed “H”.
/RD (E) and /WR (R/W) are fixed to either “H” or “L”.
With serial data input, It is impossible read data from RAM |
4 |
C86 |
I |
This is the MPU interface selection pin.
C86 = “H”: 6800 Series MPU interface.
C86 = “L”: 8080 Series MPU interface |
5 |
VR |
I |
Output voltage regulator terminal. Provides the voltage between VSS and V0 through a resistive voltage divider.
IRS = “L” : the V0 voltage regulator internal resistors are not used.
IRS = “H” : the V0 voltage regulator internal resistors are used. |
6~10 |
V0~V4 |
Power supply |
This is a multi-level power supply for the liquid crystal drive. |
11 |
VRS |
Power supply |
This is the internal-output VREG power supply for the LCD power supply voltage regulator |
12 |
CAP4+ |
O |
DC/DC voltage converter. |
13 |
CAP2- |
O |
DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2P terminal. |
14 |
CAP2+ |
O |
DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2N terminal. |
15 |
CAP1+ |
O |
DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1N terminal. |
16 |
CAP1- |
O |
DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1P terminal. |
17 |
CAP3+ |
O |
DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1N terminal. |
18 |
CAP5+ |
O |
DC/DC voltage converter. |
19 |
VOUT |
O |
DC/DC voltage converter. Connect a capacitor between this terminal and vss or VDD |
20 |
VSS |
Power supply |
Ground |
21 |
VDD |
Power supply |
Power supply |
22~29 |
D7~D0 |
I/O |
Data bus line |
30 |
/RD(E) |
I |
• When connected to 8080 series MPU, this pin is treated as the “/RD” signal of the 8080 MPU and is LOW-active.
The data bus is in an output status when this signal is “L”.
• When connected to 6800 series MPU, this pin is treated as the “E” signal of the 6800 MPU and is HIGH-active.
This is the enable clock input terminal of the 6800 Series MPU. |
31 |
/WR(R/W) |
I |
• When connected to 8080 series MPU, this pin is treated as the “/WR” signal of the 8080 MPU and is LOW-active.
The signals on the data bus are latched at the rising edge of the /WR signal.
• When connected to 6800 series MPU, this pin is treated as the “R/W” signal of the 6800 MPU and decides the access type :
When R/W = “H”: Read.
When R/W = “L”: Write.
|
32 |
A0 |
I |
This is connect to the least significant bit of the normal MPU address bus, and it determines whether the data bits are data or command.
A0 = “H”: Indicates that D0 to D7 are display data.
A0 = “L”: Indicates that D0 to D7 are control data. |
33 |
/RES |
I |
When RES is set to “L”, the setting are initialized. |
34 |
/CS1 |
I |
This is the chip select signal. |